The above referenced U.S. Pat. No. 7,248,120 discusses integrated amplifier circuits using stacked transistors, such as FET transistors, that can be used to control signals that substantially exceed the voltage withstand capability of the individual transistors of the stack. Accordingly, a stack of transistors can operate from a higher supply voltage to provide a higher output power while operating the individual transistors of the stack within their voltage withstand capabilities. A number of the transistors of the stack may be selected according to the supply voltage, the voltage withstand capability of the transistors, and a desired distribution, such as for example, an equal distribution, of the supply voltage across the transistors of the stack. Biasing of the transistors of the stack can provide the desired distribution of the supply voltage across the transistors of the stack. As an output RF signal from the stack responsive to an input RF signal may have an (AC) voltage substantially larger than the (DC) supply voltage to the stack, the above referenced U.S. Pat. No. 7,248,120 uses (bypass) gate capacitors at the gates of cascode transistors of the stack to allow the gates of the cascode transistors to “float” with the RF signal and therefore maintain a distribution of the voltage of the output RF signal across the transistors of the stack for safe operation of the transistors. As described in the U.S. Pat. No. 7,248,120, capacitance values of said gate capacitors are inversely proportional to a position of a corresponding transistor in the stack; gate capacitors of transistors of the stack have decreasing capacitance values as the transistors get closer to the output of the stack. As the number of the transistors in the stack increases, capacitance values of the gate capacitors associated to transistors closer to the output of the stack can decrease to values that may approach values corresponding to stray/parasitic capacitance in the physical layout of the amplifier circuit, thereby rendering practical realization of such circuit challenging. It is desirable to provide an alternative stack topology that allows practical realization of large stack heights in integrated circuits operable as amplifiers.